Digital Technologies Research and Applications

Review

A Comprehensive Review of Memory Architectures and Network Interfaces and Advancements in High-Bandwidth and Low-Latency Systems

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https://doi.org/10.54963/dtra.v5i2.1745
Rajeena, S., & Karimullah, S. (2026). A Comprehensive Review of Memory Architectures and Network Interfaces and Advancements in High-Bandwidth and Low-Latency Systems. Digital Technologies Research and Applications, 5(2), 63–74. https://doi.org/10.54963/dtra.v5i2.1745
Volume 5 Issue 2: June 2026 (in progress)
Copyright (c) 2026 Shaik Rajeena, Shaik Karimullah
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Authors

  • Shaik Rajeena

    Department of Electronics and Communications, Annamacharya University, Rajampet 516115, India
  • Shaik Karimullah

    Department of Electronics and Communications, Annamacharya University, Rajampet 516115, India

Received: 22 October 2025; Revised: 5 December 2025; Accepted: 19 December 2025; Published: 15 April 2026

This review discusses the significant advances in the architecture of memory systems, the enhancement of which has been among the most significant concerns in the process of creating systems with high bandwidth and low latency requirements. It has analyzed various fields that include virtually pipelined systems, millimeter-wave interface, and enhanced memory controllers, which would meet the requirements of high-performance computing (HPC). Among all the developments put in place, die-stacked DRAM (Dynamic Random Access Memory) systems offer a high bandwidth boost with the networks-on-chip scalable and meant to address the issues of congestion and incoherence in interconnecting cores. The literature survey also identifies some of the major developments in the mechanism of passing messages and memory management optimizations in distributed systems that have been found to be critical towards useful data transfer and processing in massive parallel computer systems. The advanced multi-port memory controllers are also observed to improve the bandwidth and efficiency in utilizing the resources. The review, however, points out some of the challenges that are still there, including the limitation of scalability of the centralized memory system, the latency issues of high-radix interconnects and the integration problems of heterogeneous computing systems. The evaluation highlights the need for new ways to tackle the limitations of current memory management techniques. Research will center on the possibilities of using machine learning to anticipate workloads and applying adaptive hybrid memory allocators to allocate across memory types dynamically. The goal of these techniques is to increase performance, bandwidth, latency, and energy efficiency in high-performance computing systems.

Keywords:

Networks-on-Chip Optimized Memory Management Memory Controllers Die-Stacked DRAM Distributed Systems Latency Heterogeneous Computing Environments

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